Packaging steps are performed at the wafer level (such as developing connections into the chip from external pads, molding and sealing for protection from the environment, etc.). This wafer is then cut into individual chips, a process called dicing, and the resultant “die” is then packaged by various conventional processes, including electrical connections to pins of a lead frame, sealing through embedding in a mold compound. Conventional PackagingĬonventional packaging process begins with the finished semiconductor wafer with chips imprinted. In the conventional discrete IC packaging process, the wafers are diced into individual IC chips first and then the chips are redistributed and packaged individually. Wafer level packaging (WLP) is a packaging technology where most or all of the IC packaging process steps are carried out at the wafer level. Then from wafers, chips of rectangular shape are cut or packaging is performed at wafer-level.
BURNIN BOARD FREE
A highly polished surface free of any surface damage is essential for the wafer. This wafer is a thin slice of this semiconductor material, which serves as the substrate for microelectronic devices built in and over the wafer. Dopants are added to the silicon during the growth process in order to set the resistivity of the wafer for the specific application.įrom a single crystal of silicon, thin wafers are cut with the help of a diamond saw. The starting material used for the fabrication of a wafer is monocrystalline silicon. Silicon wafers are a key component in integrated circuits. The packaged devices are retested to eliminate those devices that may have been damaged during the packaging process or put into defective packages. The chips that pass the wafer-level test are extracted and packaged.
Wafer-level testing and burn-in is applicable to:Ģ) devices sold as bare die, which are also referred to as ‘known good die’ or ‘KGD’ģ) devices intended for conventional packaging as well (used for screening purposes) The usual method for achieving highly reliable parts is through burn-in to sort out early failures. The reliability of the overall package is highly dependent upon the reliability of each bare die. By testing at the wafer-level, there is a great cost savings and much shorter cycle times before the wafer is packaged.
The wafer probe supplies electrical excitation to all the die on the wafer through hundreds or thousands of probing needles.ĭuring the WLTBI process, the wafer prober evaluates the characteristics of prototype ICs, reliability evaluation, and defect analysis at the wafer-level. The increasing complexity of SoC (System on Chip: commonly known as an “IC” or “chip”) has placed enormous demands on traditional test method due to the shrinking of the die size and as such requires better methods of ensuring reliability at the wafer level.Ī system for testing a wafer includes a testing station for applying and monitoring burn-in test signals for integrated circuits and wafer probers are used for electrical testing of wafers in the semiconductor development and manufacturing process. Wafer-level Test and Burn-in (WLTBI) refers to the process of subjecting semiconductor devices to electrical testing and burn-in while they are still in wafer form.
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